High-speed, high-resolution and low-consumption analog/digital converter with single-ended input

ABSTRACT

An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparators.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention pertains to an A/D (analog/digital)converter and more particularly to an integrated, single-ended input A/Dconverter that has a high-speed and low current consumption forgenerating a differential output.

[0003] 2. Description of the Related Art

[0004] It is very common for electronic equipment to require analogsignals to be converted into digital signals. A significant example ofthis type of equipment is provided by digital cellular telephones. Therequirements of low consumption and high performance associated withthese applications create particularly exacting conditions for thedesign of the integrated circuits that constitute the electronic systemof the equipment.

[0005] A type of A/D converter particularly advantageous for employmentin these electronic systems is the one that makes use of capacitorsweighted in binary code with associated switches that are controlled bya logic circuit in accordance with a technique known as SAR (SuccessiveApproximation Register).

[0006] When designing complex integrated circuits, it is generallysought to obtain a large dynamic range and a good immunity to noiseoriginating both within and without the integrated circuit by realizingthe part that processes the analog signal with structures of acompletely differential type.

[0007] In certain cases, however, the analog signals that have to beconverted into digital form are not of the differential type, that is tosay, in the form of voltage variations of a sign opposite to a commonreference potential, but are rather of an asymmetric or single-endedtype, i.e. in the form of a single voltage variable with respect to areference potential. In these cases the designer has two alternatives:one can either use A/D converters that function with single ended inputsignals or transform the signal into a differential signal and thenapply it to an A/D converter that functions with differential inputsignals. In the former case one has to find means, if possible, foravoiding the negative effects of noise and the other intrinsiclimitations associated with the processing of a single-ended signal,while in the latter case one has to accept a higher consumption andother undesired effects (distortion and offset) of the circuit that hasto precede the converter.

[0008] With a view to obviating the drawbacks of both thesealternatives, there has been proposed an A/D converter with single-endedinput, as described in EP-A-1039642, that presents the advantages of adifferential structure without requiring a circuit to transform thesingle-ended signal into a differential one. This known converter makesuse of four capacitance arrays in place of the two arrays provided in aconverter with a differential input, and from the constructional pointof view this means that the integrated circuit comprising the converterwill occupy a rather large area, while from the functional point of viewit brings in its wake a considerable increase in electric powerconsumption and the need for having to use a high-sensitivity comparatorto compensate the smaller voltage excursion at the comparator input.This implies a reduced operating speed or, alternately, the constructionof a comparator providing a better performance and therefore inevitablya larger size and costlier energy consumption.

BRIEF SUMMARY OF THE INVENTION

[0009] The disclosed embodiments of the present invention provide an A/Dconverter that, apart from being able to perform the direct conversionof a single ended signal and having a noise immunity at least equal tothat of a converter for differential signals, will also be capable ofbeing realized with an integrated circuit occupying a small area, have alow consumption and make possible a high operating speed without callingfor a particularly sensitive comparator.

[0010] According to the invention, a converter is provided thatincludes:

[0011] a first array of sampling capacitors weighted in binary code,each connected between a first circuit node and a central terminal of acontrolled switching device associated therewith, said device having amultiplicity of terminals selectively connectable with the centralterminal;

[0012] a second array of sampling capacitors weighted in binary code,each connected between a second circuit node and a central terminal of acontrolled switching device associated therewith, said device having amultiplicity of terminals capable of being selectively connected withthe central terminal;

[0013] reference voltage generator means comprising a common referenceterminal, a first and a second differential reference terminal, and acommon mode reference terminal;

[0014] an input terminal for analog signals referred to the voltage ofthe common reference terminal;

[0015] first and second controlled connection means connected,respectively, to the first and the second circuit node for selectiveconnection to the common mode reference terminal;

[0016] a voltage comparator having a first and a second input terminalconnected, respectively, to the first and the second circuit node, andan output terminal;

[0017] processing, control, and register means connected to the outputof the comparator, to the controlled switching devices, associated withthe capacitors and to the controlled connection means to operate saidswitching devices and said connection means in accordance with apredetermined timing program and as a function of the output of thecomparator, to memorize the states of at least some of the switchingdevices associated with the capacitors and to furnish output signalscorresponding to the analog signals applied to the input terminal;

[0018] wherein the multiplicity of selectively connectable terminals ofeach of the switching devices of the first capacitor array comprises afirst terminal connected to the input terminal and a second and a thirdterminal connected, respectively, to the first and the seconddifferential reference terminal; and

[0019] the multiplicity of selectively connectable terminals of each ofthe switching devices of the second array comprises a first terminalconnected to the common reference terminal and a second terminalconnected to the second differential reference terminal.

[0020] In accordance with another embodiment of the invention, an A/Dconverter is provided that includes a first array of sampling capacitorsweighted in binary code, each connected between a first circuit node anda central terminal of a controlled switching device associatedtherewith, said device having a multiplicity of terminals selectivelyconnectable with the central terminal; a second array of samplingcapacitors weighted in binary code, each connected between a secondcircuit node and a central terminal of a controlled switching deviceassociated therewith, said device having a multiplicity of terminalscapable of being selectively connected with the central terminal;reference voltage generator means comprising a common referenceterminal, a first and a second differential reference terminal, and acommon mode reference terminal; an input terminal for analog signalsreferred to the voltage of the common reference terminal; first andsecond controlled connection means connected, respectively, to the firstand the second circuit node for selective connection to the common modereference terminal; a voltage comparator having a first and a secondinput terminal connected, respectively, to the first and the secondcircuit node, and an output terminal; processing, control, and registermeans connected to the output of the comparator, to the controlledswitching devices, associated with the capacitors and to the controlledconnection means to operate said switching devices and said connectionmeans in accordance with a predetermined timing program and as afunction of the output of the comparator, to memorize the states of atleast some of the switching devices associated with the capacitors andto furnish output signals corresponding to the analog signals applied tothe input terminal; wherein the multiplicity of selectively connectableterminals of each of the switching devices of the first capacitor arraycomprises a first terminal connected to the input terminal and a secondand a third terminal connected, respectively, to the first and thesecond differential reference terminal; and the multiplicity ofselectively connectable terminals of each of the switching devices ofthe second array comprises a first terminal connected to the commonreference terminal and a second terminal connected to the seconddifferential reference terminal.

[0021] In accordance with yet a further embodiment of the invention, ananalog-to-digital converter is provided that includes a first capacitivearray comprising a plurality of capacitors each having a first terminalcoupled to a first node and a second terminal selectively coupleable toone of an input terminal, a first reference terminal, and a secondreference terminal; a second capacitive array comprising a plurality ofcapacitors, each capacitor having a first terminal coupled to a secondnode and a second terminal selectively coupleable to one of a commonreference terminal and the second reference terminal; a comparatorhaving a first input coupled to the first node, a second input coupledto the second node, and a first output selectively coupleable to thefirst node, a second output selectively coupleable to the second node,and a third output; a first supplementary capacitor having a firstterminal coupled to the first node and a second terminal selectivelycoupleable to one from among the first reference terminal and the secondreference terminal, and a second supplemental capacitor having a firstterminal coupled to the second node and a second terminal selectivelycoupleable to one of the first reference terminal and the secondreference terminal; a processing circuit having an input coupled to thethird output of the comparator, and an output for generating digitaloutput signals in response to analog input signals received at the inputterminal; and control outputs coupleable to the first and secondcapacitive arrays and the first and second supplemental capacitors uponwhich are generated control signals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The invention will be more clearly understood from the detaileddescription about to be given of some embodiments thereof, which are tobe considered as examples and not limitative in any way, saiddescription making reference to the attached drawings of which:

[0023]FIG. 1 shows an A/D converter for single-ended signals of theknown type and operating in accordance with SAR technique;

[0024]FIG. 2 shows the schematic circuit diagramme of an A/D converterfor single-ended signals that uses a circuit for transformingsingle-ended signals into differential signals;

[0025]FIG. 3 shows the schematic circuit diagramme of an A/D converterfor single-ended signals in accordance with a first embodiment of theinvention;

[0026]FIG. 4 shows a second embodiment of the invention and

[0027]FIG. 5 shows a third embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] For the sake of simplicity of representation, the figures showconverters that convert an analog signal by sampling it with binarynumbers consisting of only five bits, but in actual practice it isclearly possible to realize converters with a much larger number ofbits.

[0029] The circuit diagramme of FIG. 1 shows an array—indicated by thereference number 10—of six capacitors b1-b6, each of which is associatedwith one of the switches SW1-SW6. The capacitors from b5 to b1 areweighted in binary code, i.e. have capacitance values that increase inaccordance with the factor 2^(i), where i=0, 1, 2, 3, 4. The sixthcapacitor b6, which has the same capacitance as capacitor b5, serves tomake the sum of the capacitances of the array exactly equal to twice thecapacitance of capacitor b1.

[0030] One electrode of each of the capacitors is connected to a commonterminal NS. The switches serve to connect the other electrode of eachof the capacitors selectively to either a first terminal, indicated byNC, or to a second terminal, indicated by the ground symbol. Theterminal NS may either be connected to ground or left free by means of aswitch S2. By means of a switch S1, the terminal NC can be selectivelyconnected either to an input terminal 11, to which there is applied aninput signal Vin (a potential with respect to ground), or to a referenceterminal 12, to which there is applied a reference potential Vref.

[0031] The terminal NS is connected to the non-inverting input terminalof an operational amplifier 13 that acts as a comparator. The invertingterminal of operational amplifier 13 is connected to ground. The outputOutCmp of the comparator is connected to a processing, control andregister unit that is indicated by the reference number 17, said unitcomprising a logic control unit 14, a register 15 and a circuit 16 forreading the register. More particularly, the output OutCmp is connectedto the logic control unit 14 that, in its turn, is connected to theswitches SW1-SW6, the switch S2 and the switch S1 and operates them inaccordance with a predetermined timing program and the comparatoroutput. It will be understood that the switches in actual practiceconsist of controllable electronic connection devices such as MOStransistors or combinations of MOS transistors. The logic unit 14 isalso connected to the register 15, which serves to memorize the positionof the switches SW1-SW5. The register reading circuit 16 provides as itsoutput a digital signal Nout corresponding to the analog input signalVin. A converter similar to the one of FIG. 1 is described, for example,in “Analog MOS Integrated Circuits” by Gregorian and Temes, published byWILEY, pp. 420-425.

[0032] Put very briefly, the converter operates as follows:

[0033] In a first phase the switches are controlled by the logic unit 14in such a manner as to be in the positions shown in FIG. 1, i.e. withthe terminal NC connected via the switch S1 to input terminal 11, towhich there is applied the signal Vin to be converted, with the terminalNS connected via the switch S2 to ground and with all the lowerelectrodes of the capacitors connected via their associated switchesSW1-SW6 to the terminal NC, so that all the capacitors are charged tothe voltage Vin.

[0034] In the next phase the logic unit 14 causes switch S2 to open andthen operates the switches SW1-SW6 in such a manner as to connect thelower electrodes of all the capacitors to ground, with the result thatthe common terminal NS of array 10 will be charged to the voltage −Vin.

[0035] At this point logic unit 14 starts the typical operations of theSAR technique aimed at identifying—one after the other—the bit valuesthat make up a binary number that represents the sample of the inputvoltage; more particularly:

[0036] With a view to finding the most significant bit, the switches SW1and S1 are operated to connect the lower electrode of capacitor b1 ofthe greatest capacitance (C) to terminal 12, which is at the referencevoltage Vref. This causes the voltage of the terminal NS to be raisedfrom −Vin to −Vin+Vref/2. The reference voltage Vref is chosen so as tobe equal to the maximum voltage Vin to be converted.

[0037] If the voltage −Vin+Vref/2 is negative, comparator 13 willprovide a low output signal, and the logic unit 14 will maintain theswitch SW1 in the position in which the lower electrode of the capacitorb1 is connected to the reference terminal 12 (Vref) and will transmitthis position information to the register 15 as corresponding to a bit1:

[0038] When the voltage −Vin+Vref/2 is positive, comparator 13 will havea high output signal and the logic circuit 14 will bring the switch SW1back into the position in which the capacitor b1 is connected to groundand will transmit this position information to the register 15 ascorresponding to a bit 0.

[0039] The same operation will be performed for the capacitor b2 to findthe second bit, and so on for all the remaining capacitors, with theexclusion of only the last one, b6, which remains connected to groundfor the entire duration of the SAR operations.

[0040] At the end of the operation the register 15 will contain fivebits that represent the final positions of the switches SW1-SW5 and thebinary code corresponding to the measurement of the sample of the inputvoltage Vin.

[0041] As mentioned at the beginning, the operation of a single-endedA/D converter like the one that has just been described can benegatively affected by noise. Indeed, it should be noted that thereference voltage Vref, which is usually generated by a circuit situatedon the same substrate on which there is formed the converter with theother analog and digital circuits, is subject to the noise of the supplyvoltage and the noise that the other circuits induce in the substrate.Similarly, any noise present at the ground terminal at the moment whenthe switch S2 is opened will be memorized on the terminal NS.Furthermore, the capacitance that the switch S2 (normally an MOStransistor) assumes with respect to the terminal NS will becomedischarged when the switch opens, thus causing a voltage variation ofthe terminal NS (the so-called feed-through effect). This variationgives rise to a conversion offset, that is to say, a component that isnot due to the input signal and may prejudice the accuracy of theconversion.

[0042] With a view to avoiding these difficulties, as already mentionedat the beginning, it has been proposed to transform the single-endedsignal into a differential signal and then to perform the conversionwith a differential converter. A circuit structure realizing thisproposal is schematically illustrated in FIG. 2.

[0043] The analog signal to be converted, indicated once again by Vin,is applied to the input of a circuit 20 capable of transforming asingle-ended input voltage into two differential output voltages +Vinand −Vin (in the figure SE→FD means single-ended to fully differential).In actual practice the circuit 20 could consist substantially of anoperational amplifier with an appropriate feedback.

[0044] Applied to circuit 20 is a so-called common mode voltage Vcm,which constitutes the reference voltage of the differential outputvoltages +Vin and −Vin. The differential output voltages +Vin and −Vinare applied via a switch S1A, S1B to two capacitors arrays 10A and 10B,equal to the array 10 of FIG. 1 except for the fact that the terminalscorresponding to the terminals connected to ground are at the commonmode voltage Vcm and those corresponding to the terminal connected tothe reference voltage Vref are at a differential voltage that has apositive value (+Vref) and a negative value (−Vref) with respect to thecommon mode voltage Vcm. The common terminals NS+ and NS− of the twoarrays are connected, respectively, to the non-inverting and theinverting terminal of a comparator 23 similar to the comparator 13 ofFIG. 1.

[0045] A logic unit 14′ controls the switches in accordance with aprogram that is altogether analogous to the one utilized by the logicunit 14 of FIG. 1. It should however be noted that the switches ofcapacitor array 10A are controlled at the same time as the correspondingswitches of capacitor array 10B and that the reference voltages areapplied in push-pull mode, that is to say, whenever a capacitor of array10A is at Vref, its counterpart in array 10B is at −Vref. A register 15′and a register reading unit 16′ similar to those indicated by thereference numbers 15 and 16 of FIG. 1, as well as the logic unit 14′,form part of a processing, control and register unit 17′ similar to theone indicated by 17 of the converter in accordance with FIG. 2.

[0046] The converter described above makes it possible to obtain a goodnoise immunity. Indeed, any noise superposed on the common mode voltageVcm will be memorized in an identical manner by the two capacitor arrays10A and 10B, so that the voltage difference between the terminals NS+and NS−, which are also the input terminal of the converter, will not beaffected by the noise. During the successive approximation phase,moreover, the number of capacitors of array 10A connected to Vcm via therespective switches associated with them will be equal to the number ofcapacitors of array 10B connected to Vcm and the capacitors connected to+Vref or −Vref will have their homologous capacitors connected to,respectively, Vref or +Vref. Since the reference voltage is differentialand the interferences are in a common mode, any interference thataffects Vcm and ±Vref will have practically no effect on the precisionof the conversion.

[0047] As already mentioned at the beginning, the converter inaccordance with FIG. 2 is associated with some drawbacks deriving fromthe addition of circuit 20 that transforms the single-ended signal intoa completely differential one, drawbacks that to some extent nullify theadvantages of the conversion into differential form and include greaterenergy consumption, distortion of the signal that is to be converted,and conversion offset.

[0048] The A/D converter in accordance with the embodiment of theinvention shown in FIG. 3 has a first capacitor array indicated by thereference number 10A′ and the expression Array Vin, which is equal toarray 10A of FIG. 2, and a second capacitor array indicated by thereference number 10B′ and the expression Array Vrefm, which is equal toarray 10B of FIG. 2, as well as a voltage comparator 23″ and aprocessing, control and register unit 17″ comprising a logic unit 14″, aregister 15″ and a reading unit 16″ like the converter of FIG. 2, butdiffers from the known converter in several important respects. Moreparticularly, the switches of array 10A′, indicated by S1-S6, arethree-way switches, each with a central terminal, connected to acapacitor of the array, which can therefore be selectively connected toone of three terminals, namely the input terminal of the converter, i.e.the output of a source of voltage signals that have to be converted(Vin), and a first and second reference terminal, i.e. the outputs of anappropriate reference voltage source (Vrefp, Vrefm). The switchesS1m-S6m of array 10B′ are two-way switches like those of array 10B ofthe circuit of FIG. 2 and connect the capacitors selectively to one orthe other of two terminals connected, respectively, to the groundterminal (Gnd) and the second reference terminal Vrefm. As can be seen,there are no switches similar to those indicated by S1A and S1B in FIG.2, nor is there a circuit to transform the single-ended input signalinto a differential signal. The identically weighted capacitors of thetwo arrays 10A′ and 10B′ are preferably equal to each other, but theinvention may also be advantageously implemented with capacitors thatare not wholly identical.

[0049] The voltages Vrefp and Vrefm are two differential referencevoltages referred to the common mode voltage Vcm. Vcm will preferably besituated at the centre of the range defined by Vrefp and Vrefm. Solelyfor indicative purposes, the following values might be associated withan integrated circuit where the supply voltage Vdd=2.5 Volt: Vrefp=2Volt, Vrefm=0.5 Volt, and Vcm=1.25 Volt. The ground terminal Gnd is thecommon reference terminal of the integrated circuit and coincides withthe lower-voltage terminal of the supply source, assumed to be equal tozero. The voltage signals Vin are referred to the ground potential andmay assume values comprised between 0 and Vrefp-Vrefm.

[0050] Let us now consider the actual functioning of the converter inaccordance with the invention as represented in FIG. 3. In the initialcharging phase the logic unit 14″ generates control signals such thatthe switches SP and SM will be closed, while all the switches S1-S6 ofarray 10A′ will be in the position in which they connect the capacitorsto the terminal Vin and all the switches S1 m-S6 m of array 10B′ will bein the position in which they connect the capacitors to the groundterminal Gnd. In this phase the capacitors of array 10A′ become chargedto the voltage Vcm-Vin and the capacitors of array 10B′ become chargedto the voltage Vcm.

[0051] The conversion by means of the SAR technique briefly described inconnection with FIG. 1 commences in the next phase: The switches SP andSM are opened, the switch S1 associated with the most highly weightedcapacitor (C) is brought into the position in which it connects to theterminal Vrefp, the switches S2-S6 are brought into the position inwhich the capacitors associated with them are connected to the terminalVrefm and the switches S1 m-S6 m are likewise connected to the terminalVrefm. This operation brings the node NS+ to the voltageVcm−Vin+Vrefm/2+Vrefp/2 and the node NS− to the voltage Vcm+Vrefm.Applying the example values mentioned above, the node NS+ will thus beat (2.5−Vin) Volt and the node NS− at 1.75 Volt. If the differencebetween the voltages at the nodes NS+ and NS− (−Vin+Vrefp/2, i.e. 0.75Volt−Vin) is negative, the switch S1 will remain in the position inwhich it connects to the terminal Vrefp, and the register 15″ willrecord this position information as corresponding to a bit 1; but if itis positive, the logic unit 14″ will bring switch S1 into the positionin which it connects to the terminal Vrefm and will transmit thisposition information to the register 15″ as corresponding to a bit 0.

[0052] A similar operation is carried out for the capacitor of the nexthighest weighting (C/2) to find the second most significant bit and soon for all the remaining capacitors, excluding only the last (C/16),which remains connected to the terminal Vrefm for the entire duration ofthe SAR operation. During these operations the switches S1 m-S6 m remainin the position that connect them with the terminal Vrefm.

[0053] The converter just described has numerous advantages as comparedwith the prior art. First of all, it should be noted that during thephase of charging to the voltage Vin the array 10A′ is connected betweenVcm and Vin and the array 10B′ is connected between Vcm and ground:since the voltage Vin is referred to ground, possible interferencestending to vary the ground potential will have no effect at all, becausethe capacitors of array 10B′ will be charged to a voltage determined bythe effective swing of the input signal between the effective groundpotential and Vin, and the capacitors of array 10A′ will be charged to avoltage referred to the same effective ground potential. Furthermore,during the SAR conversion operations one of the terminals of thecapacitors of array 10A′ is brought to the voltage Vrefp or Vrefm andone terminal of the capacitors of array 10B′ is maintained at thevoltage Vrefm. Since the reference voltages Vrefp and Vrefm aregenerated by a differential structure, any interferences will becomesuperposed with the same sign on both the reference voltages, i.e. theywill have the same effect on both comparator inputs and, consequently,will not in any way alter the measurement.

[0054] The circuit therefore complies with the aim of obtaining thedirect conversion of a single-ended analog signal by means of astructure that has all the advantageous characteristics of a structurefunctioning with differential inputs. It should be noted that thisresult is obtained without adding any capacitive elements as has to bedone, for example, in the case described in EP-A-1039642 and withouthaving to use particularly sensitive comparators, since the inputvoltage Vin is not reduced by capacitive dividers and is therefore atits highest possible value. Moreover, the consumption is very small andthe source of the reference voltages Vrefp and Vrefm does not need anoutput buffer of greater power than is usually required for a completelydifferential comparator in the same operating conditions, because thecapacitive charges are only those of the two capacitor arrays 10A′ and10B′.

[0055] The embodiment described in FIG. 3 will perform best inapplications in which the lower reference voltage (Vrefm) is close toground potential, because the common mode voltage at which thecomparator 23′ works is not Vcm, as would be desirable in order to havethe maximum switching speed, but rather Vcm+Vrefm. However, action canbe taken to fix the common mode voltage to Vcm at the expense of a smallreduction of the dynamic range of the comparator input. As shown in FIG.4, for example, each of the nodes NS+ and Ns− can be connected to acapacitor Cx that can be switched by means of respective switches SCxP,ScxM between the two reference voltages Vrefp and Vrefm. The switchesSCxP and ScxM are controlled by the logic unit, here indicated by 14′″,in such a way as to connect the two capacitors Cx to the terminal Vrefpduring the charging of the capacitors of array 10A, to the input voltageVin and to the terminal Vrefm during the SAR conversion operations. Ifthe common mode voltage of the comparator is to be substantiallymaintained at the predetermined value Vcm, the capacitance of each ofthe capacitors has to be Cx=2C*(Vrefm)/(Vrefp−Vrefm).

[0056] According to a variant that can be used to good advantage whenthe supply voltage of the integrated circuit can be chosen within anarrow range, the capacitors may be switched between the extremes Vddand Gn of the supply voltage rather than between Vrefp and Vrefm. Inthis case the capacitance of the two capacitors has to beCx′=2C*(VrefmNdd). This variant has the advantage that no capacitancesremain connected to the source of the differential voltages Vrefp, Vrefmwhile the array 10A′ is being charged to the input voltage Vin.

[0057]FIG. 5 shows a variant of the converter of FIG. 4 that utilizes anexpedient that could be used also with the converter of FIG. 3 and makesit possible to do without an external source of the common mode voltage(Vcm), because this voltage is generated by the comparator itself. Thelatter is to all intents and purposes a fully-differential amplifierthat has two switches S2RA and S2RB between the differential inputs andoutputs. This configuration of the comparator, though known as such,serves to annul the comparator offset by means of the simultaneousclosure of the two switches. When the two switches are closed, thecomparator inputs, and therefore also the nodes NS+ and NS−, are forcedto the common mode voltage Vcm of the comparator. Given an appropriatecomparator design, this voltage is chosen to have the value needed forthe correct charging of the capacitor array 10A′. It should be notedthat the switches S2RA and S2RB, which are operated in accordance withthe same timing program used for the switches SP and SM of FIG. 4, areclosed only during the charging phase and remain open during the SARconversion phase.

[0058] To conclude, a single-ended signal can be converted with theutmost precision, because the converter is as insensitive tointerferences acting on the supply source and the sources of thereference voltages as it would be if a differential signal were to beconverted. This is obtained without using a circuit to transform thesingle-ended signal into a differential one and without additionalcapacitor arrays, and therefore also without any supplementary energyconsumption and without a greater area being occupied in the integratedcircuit. In the third embodiment, the one shown in FIG. 5, the energyand area savings are even greater on account of the fact that it doesnot need a specific circuit for generating the common mode referencevoltage.

[0059] It is also clear to a person skilled in the art that theteachings derived from acquaintance with the embodiments of theinvention described hereinabove can be applied with the same or evengreater advantages to the realization of A/D converters that sample witha number of bits greater than five, for example, by utilizing the knowntechnique of dividing the capacitances into an“upper array” and a “lowerarray”, which makes it possible to interrupt the exponential growth ofthe capacitance values.

[0060] All of the above U.S. patents, U.S. patent applicationpublications, U.S. patent applications, foreign patents, foreign patentapplications and non-patent publications referred to in thisspecification and/or listed in the Application Data Sheet, areincorporated herein by reference, in their entirety.

[0061] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. An A/D converter, comprising: a first array of sampling capacitorsweighted in binary code, each connected between a first circuit node anda central terminal of a controlled switching device associatedtherewith, said device having a multiplicity of terminals selectivelyconnectable with the central terminal; a second array of samplingcapacitors weighted in binary code, each connected between a secondcircuit node and a central terminal of a controlled switching deviceassociated therewith, said device having a multiplicity of terminalscapable of being selectively connected with the central terminal;reference voltage generator means comprising a common referenceterminal, a first and a second differential reference terminal and acommon mode reference terminal; an input terminal for analog signalsreferred to the voltage of the common reference terminal; first andsecond controlled connection means connected, respectively, to the firstand the second circuit node for selective connection to the common modereference terminal; a voltage comparator having a first and a secondinput terminal connected, respectively, to the first and the secondcircuit node, and an output terminal; processing, control, and registermeans connected to the output of the comparator, to the controlledswitching devices, associated with the capacitors and to the controlledconnection means to operate said switching devices and said connectionmeans in accordance with a predetermined timing program and as afunction of the output of the comparator, to memorize the states of atleast some of the switching devices associated with the capacitors andto furnish output signals corresponding to the analog signals applied tothe input terminal, wherein the multiplicity of selectively connectableterminals of each of the switching devices of the first capacitor arraycomprises a first terminal connected to the input terminal and a secondand a third terminal connected, respectively, to the first and thesecond differential reference terminal; and the multiplicity ofselectively connectable terminals of each of the switching devices ofthe second array comprises a first terminal connected to the commonreference terminal and a second terminal connected to the seconddifferential reference terminal.
 2. The converter of claim 1 wherein thecapacitors of the same weighting of the first and the second array aresubstantially equal to each other.
 3. The converter of claim 1,comprising a first and a second supplementary capacitor connected,respectively, between the first or the second circuit node and thecentral terminal of a respective two-way switch controlled by thecontrol, processing and register means to selectively connect saidcentral terminal to the first or the second differential referenceterminal.
 4. The converter of claim 1, comprising a first and a secondsupplementary capacitor connected, respectively, between the first orthe second circuit node and the central terminal of a respective two-wayswitch controlled by the control, processing and register means toselectively connect said central terminal to a first or a secondterminal of a supply voltage source.
 5. The converter of claim 1 whereinthe common mode voltage source is comprised within the comparator. 6.The converter of claim 5 wherein the comparator has a first and a seconddifferential output terminal and wherein the first and the secondcontrolled connection means connected, respectively, to the first andthe second circuit node are connected, respectively, between the firstnode and the first differential output and between the second node andthe second differential output.
 7. An A/D converter, comprising: a firstcapacitor array, each capacitor in the first capacitor array having afirst terminal coupled to a first node and a second terminal selectivelyconnectable to one of an input terminal, a first reference terminal, anda second reference terminal; a second capacitor array, each capacitor inthe second capacitor array having a first terminal coupled to a secondnode and a second terminal selectively connectable to one of a commonreference terminal and the second reference terminal; first and secondswitches for selectively coupling the first and second nodes,respectively, to a common mode reference terminal; a comparator having afirst input coupled to the first node, a second input coupled to thesecond node, and an output; and a processing circuit coupled to theoutput of the comparator and further coupled to the first and secondcapacitor arrays and configured to generate an output signal in responseto an output of the comparator and to generate control signals toselectively connect the capacitors in the first capacitor array to oneof the input terminal, first reference terminal, and second referenceterminal, and to selectively connect the capacitors in the secondcapacitor array to one of the common reference terminal and the secondreference terminal.
 8. The converter of claim 7 wherein a common modevoltage source is coupled to the common mode terminal and is comprisedwithin the comparator.
 9. The converter of claim 7 wherein the first andsecond switches are controlled by the processing circuit.
 10. Theconverter of claim 9, further comprising a first capacitive devicehaving a first terminal coupled to the first node and a second terminalselectively coupleable to one of the first reference terminal and thesecond reference terminal and a second capacitive device having a firstterminal coupled to the second node and a second terminal selectivelycoupleable to one of the first reference terminal and the secondreference terminal.
 11. The converter of claim 10 wherein the first andsecond capacitive devices have control terminals coupled to theprocessing circuit to receive control signals therefrom.
 12. Theconverter of claim 11 wherein the processing circuit is configured tocontrol the first and second capacitive arrays and the first and secondcapacitive devices in accordance with a predetermined timing program andas a function of the output of the comparator.
 13. An analog-to-digitalconverter, comprising: a first capacitive array comprising a pluralityof capacitors, each capacitor having a first terminal coupled to a firstnode and a second terminal selectively coupleable to one of an inputterminal, a first reference terminal, and a second reference terminal; asecond capacitive array comprising a plurality of capacitors, eachcapacitor having a first terminal coupled to a second node and a secondterminal selectively coupleable to one of a common reference terminaland the second reference terminal; a comparator having a first inputcoupled to the first node, a second input coupled to the second node,and a first output selectively coupleable to the first node, a secondoutput selectively coupleable to the second node, and a third output; afirst supplementary capacitor having a first terminal coupled to thefirst node and a second terminal selectively coupleable to one of thefirst reference terminal and the second reference terminal, and a secondsupplemental capacitor having a first terminal coupled to the secondnode and a second terminal selectively coupleable to one of the firstreference terminal and the second reference terminal; a processingcircuit having an input coupled to the third output of the comparator,and an output for generating digital output signals in response toanalog input signals received at the input terminal, and control outputscoupleable to the first and second capacitive arrays and the first andsecond supplemental capacitors upon which are generated control signals.14. The converter of claim 13 wherein the first output of the comparatoris selectively coupled to the first node by a feedback switch controlledby the processing circuit, and the second output of the comparator isselectively coupled to the second node by a second feedback switchcontrolled by the processing circuit.
 15. The converter of claim 14wherein the processing circuit is configured to control the first andsecond capacitive arrays and the first and second capacitive devices inaccordance with a predetermined timing program and as a function of theoutput of the comparator.
 16. The converter of claim 15, furthercomprising a plurality of switches in the first and second capacitivearrays, each switch having a first terminal coupled to the secondterminal of a respective capacitor in the first and second capacitivearrays, a control terminal coupled to the processing circuit, and asecond terminal for selectively coupling the capacitor to a respectiveone of the input terminal, the first reference terminal, and the secondreference terminal.
 17. The converter of claim 13 wherein each of thecapacitors of the first and second capacitive arrays comprise samplingcapacitors weighted in binary code.
 18. The converter of claim 17wherein the capacitors of the same weighting of the first and secondcapacitive arrays are substantially equal to each other.